This invention relates generally to non-volatile flash memory systems, and, more specifically, to a structure and process of forming arrays of memory cells that utilize substrate trenches to reduce the overall size of the arrays.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells. Arrays with either a NOR or a NAND architecture are commonly used. One or more integrated circuit chips containing a memory cell array are commonly combined with a controller chip to form a complete memory system. Alternatively, part or all of the controller function may be implemented on the same chip that contains all or part of the memory cell array.
In one type of NOR array, each memory cell has a “split-channel” between source and drain diffusions. The floating gate of the cell is positioned over one portion of the channel and the word line (also referred to as a control gate) is positioned over the other channel portion as well as over the floating gate. This effectively forms a cell with two transistors in series, one (the memory transistor) with a combination of the amount of charge on the floating gate and the voltage on the word line controlling the amount of current that can flow through its portion of the channel, and the other (the select transistor) having the word line alone serving as its gate. The word line extends over a row of floating gates. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, and 6,281,075.
A modification of this split-channel flash EEPROM cell adds a steering gate positioned between the floating gate and the word line. Each steering gate of an array extends over one column of floating gates, perpendicular to the word lines. The effect is to relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the floating gate to a desired level through an electric field (capacitive) coupling between the word line and the floating gate. It is often difficult to perform both of these functions in an optimum manner with a single voltage. With the addition of the steering gate, the word line need only perform function (1), while the added steering gate performs function (2). The use of steering gates in a flash EEPROM array is described, for example, in U.S. Pat. Nos. 5,313,421 and 6,222,762.
In one specific type of memory cell that efficiently utilizes integrated circuit area, two floating gates are included, each of which may be operated in binary (one bit per floating gate) or with multiple programming states (more than one bit per floating gate). The two floating gates are positioned over the substrate channel between source and drain diffusions with a select transistor in between them. A steering gate is included along each column of floating gates and a word line is provided thereover along each row of floating gates. When accessing a given floating gate for reading or programming, the steering gate over the other floating gate of the cell containing the floating gate of interest is raised sufficiently high to turn on the channel under the other floating gate no matter what charge level exists on it. This effectively eliminates the other floating gate as a factor in reading or programming the floating gate of interest in the same memory cell. For example, the amount of current flowing through the cell, which can be used to read its state, is then a function of the amount of charge on the floating gate of interest but not of the other floating gate in the same cell.
Examples of an array with dual floating gate memory cells, and operating techniques therefore, are described in U.S. Pat. Nos. 5,712,180, 6,103,573 and 6,151,248. The dual floating gate memory cell arrays are usually formed entirely on a surface of a semiconductor substrate. However, U.S. Pat. No. 6,151,248 additionally describes, primarily with respect to FIGS. 6 and 7 thereof, memory cells formed in a trench in the substrate surface and along surface areas of the substrate adjacent to the trench. U.S. Pat. No. 6,936,887 also describes an array of memory cells partially formed in substrate trenches.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells in a row direction, across a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, 6,522,580, 6,888,755 and 6,925,007.
There are various programming techniques for causing electrons to travel through the gate dielectric from the substrate onto the floating gate. The most common programming mechanisms are described in a book edited by Brown and Brewer, “Nonvolatile Semiconductor Memory Technology,” IEEE Press, section 1.2, pages 9-25 (1998). One technique, termed “Fowler-Nordheim tunneling” (section 1.2.1), causes electrons to tunnel through the floating gate dielectric under the influence of a high field that is established thereacross by a voltage difference between the control gate and the substrate channel. Another technique, channel hot electron injection in the drain region, commonly referred to as “hot-electron injection” (section 1.2.3), injects electrons from the cell's channel into a region of the floating gate adjacent the cell's drain. Yet another technique, termed “source side injection” (section 1.2.4), controls the substrate surface electrical potential along the length of the memory cell channel in a manner to create conditions for electron injection in a region of the channel away from the drain. Source side injection is also described in an article by Kamiya et al., “EPROM Cell with High Gate Injection Efficiency,” IEDM Technical Digest, 1982, pages 741-744, and in U.S. Pat. Nos. 4,622,656 and 5,313,421. In a further programming technique, termed “ballistic injection” high fields are generated within a short channel to accelerate electrons directly onto the charge storage element, as described by Ogura et al., “Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash”, IEDM 1998, pages 987-990.”
One of two techniques for removing charge from floating gate charge storage elements to erase memory cells are primarily used in both of the two types of memory cell arrays described above. One is to erase to the substrate by applying appropriate voltages to the source, drain, substrate and other gate(s) that cause electrons to tunnel through a portion of a dielectric layer between the floating gate and the substrate.
The other erase technique transfers electrons from the floating gate to another gate through a tunnel dielectric layer positioned between them. In the first type of cell described above, a third gate is provided for that purpose. In the second type of cell described above, which already has three gates because of the use of a steering gate, the floating gate is erased to the word line, without the necessity to add a fourth gate. Although this later technique adds back a second function to be performed by the word line, these functions are performed at different times, thus avoiding the necessity of making compromises to accommodate the two functions. When either of these erase techniques is utilized, a large number of memory cells are grouped together into blocks of a minimum number of cells that are simultaneously erased, in a “flash.” In one approach, the individual blocks include enough memory cells to store the amount of user data stored in a disk sector, namely 512 bytes, plus some overhead data. Erasure of a number of blocks at once, defect management and other flash EEPROM system features are described in U.S. Pat. No. 5,297,148. In another approach, each group contains enough cells to hold several thousand bytes of user data, equal to 8, 16 or more host sectors' worth of data that are individually programmable and readable. Examples of operating such a large block memory are given in U.S. Pat. No. 6,968,421.
In place of electrically conductive floating gates, some flash memories utilize a non-conductive dielectric material that traps electrons. In either case, an individual memory cell includes one or more charge storage elements. Examples of the use of dielectric are described in aforementioned U.S. Pat. No. 6,925,007 and documents referenced therein. In the case of a dielectric trapped charge memory cell, two or more charge storage elements may be formed as two or more regions of a single continuous layer of dielectric that are spaced apart thereacross. One example of a suitable charge storage dielectric material is a three-layer oxide-nitride-oxide (ONO) composite. Another example is a single layer of silicon rich silicon dioxide material. As in almost all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM systems. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. Another way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a memory cell threshold voltage range into more than two states. The use of four such states allows each charge storage element to store two bits of data, eight states stores three bits of data per charge storage element, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, as examples.